MOUNTAIN VIEW, Calif., May 17, 2016 – Palma Ceia SemiDesignTM (“PCS”), a provider of analog and RF IP for next-generation WiFi and mobile communications, today announced it taped out an 802.11ax analog frontend (AFE) for next next-generation WiFi access points. The AFE includes analog-to-digital converter (ADC), digital-to-analog converter (DAC) and Baseband PLL (BB-PLL) core IPs designed for manufacture using the TSMC 28HPC process node.
“Completing the first implementation of this low-power, high-performance analog frontend intended for commercial availability – in record time – establishes Palma Ceia as the market leader for analog and RF IP needed for next generation WiFi chipsets,” said James E. Flowers, co-founder & chief operating officer of Palma Ceia. “This IP, targeted for TSMC’s 28HPC process node and currently on an MPW for silicon verification, is a standard CMOS implementation designed for SoC integration. It features an ultra-low power DAC, high dynamic range ΣΔ ADC, and a low-jitter baseband clock.”
Specific features of the PCS 802.11ax analog front end:
The ADC features low signal-swing, 70dB SNDR, support for DPD, and an integrated CIC/decimator, drawing just 8mA from 0.9V and 8.5mA frm 1.25V supplies.
The current steering DAC features 12-bit resolution and draws just 6mA at 1.25V.
The PLL features a lock time of 50uS and an outstanding jitter of 0.4pS.
A follow-on to the 802.11ac Wi-Fi standard, 802.11ax delivers faster, even gigabit-speed, connections to individual devices rather than simply improving overall network capacity. This is accomplished by using MIMO (multiple-input-multiple-output) spatial streams, with each stream multiplexed with OFDA (orthogonal frequency division access). Though the focus for 802.11ax deployment is the existing 2.4 GHz and the 5 GHz unlicensed bands, additional bands between 1 GHz and 6 GHz may be added as they become available. Complete ratification of 802.11ax is expected in 2019.